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4-297 programmable peripheral application note 042 four axis stepper motor control using a programmable psd5xx mcu peripheral from wsi, inc. by nasser pooladian, data card corp. introduction the design of a stepper motor control requires various timers and electronic controls. this application note explains the basic operation of a stepper motor. it also presents the theory, implementation and electronic control of a four axis stepper motor control using the psd5xx family of products from the wsi inc. the psd5xx, as a field programmable microcontroller peripheral device, provides a high degree of integration on the embedded controller design. configuration of the memory, ease of interface to various different microcontroller buses, interrupt handling, i/o ports, and four sixteen bit counter/timers make this device a great candidate for embedded applications. a stepper motor is basically a rotational actuator which rotates a fixed anglewhen excited. a stepper motor can be directly controlled electronically without the need for a feedback element (encoder, tachometer feedback, etc.) as required in servo applications. the simpler drive and control electronics needed by a stepper motor makes it a good candidate for a positioning actuator in many different motion control applications. several different types of stepper motors are used in the industry. a hybrid stepping motor is used in this application. the rotor and stator are multi-toothed in a hybrid stepping motor and the rotor is magnetized in the axis of the rotor shaft. when properly driven, a hybrid stepping motor will step 1.8 degrees in the full step mode and 0.9 degrees in the half step mode. figure 1 shows a typical hybrid motor. stepper motor operation figure 1. hybrid stepping motor return to main menu
4-298 psd5xx ?application note 042 stepper motor operation (cont.) the stator windings in a hybrid stepper motor are distributed in 90-degree quadrants around the motor case. see figure 1 for the phase winding distribution of the hybrid motor. different methods are used for the excitation of a stepper motor. in this application a bipolar drive circuit is used for the power stage. the motor windings are connected 90 degrees apart such that the stepper motor looks like a two-phase motor. in this case there are four motor leads to be powered from the amplifier stage. each phase of this stepper motor is powered by an h bridge. figure 2 shows a typical h bridge that drives a stepper motor and figure 3 illustrates the driving waveforms. +v q1 q2 q3 q4 phase a q1 q2 q3 q4 phase b +v figur e 2. t wo h bridges for driving a t wo phase stepper motor . q1 and q4 on q1 and q4 on q2 and q3 on q1 and q4 on q2 and q3 on q1 and q4 on phase a phase b 90 phase shift figur e 3. phase excitation in a bipolar stepping motor .
psd3xx ?application note 042 4-299 stepper motor operation (cont.) phase timing for a stepper motor could be designed by either a combination of logic and linear electronics or by some stepper motor control ic? such as the l297 stepper motor controller. figure 4 shows a block diagram of a stepper motor control and the l297 is used as the stepper motor control ic. the l297 provides control to an amplifier in the current mode. the chop frequency for the l297 is set to 20khz. chop frequency is used to regulate the amount of current in the motor windings. the current reference to the motor windings is set by a pair of resistors. the l297 is configured to full step mode. the enable/disable and axis direction control are controlled from port b of the psd503b1. an electrical schematic using the l297 is given in figure 13. phase a control phase b control bridge control sense phase 1 sense phase 2 phase b phase a power bridge current sense direction clock enable figur e 4. simplified block diagram for a stepper motor contr ol
4-300 psd5xx ?application note 042 stepper motor clock generation by using a psd5xx figure 5 shows a timing diagram for the control of the phases in a stepper motor control where the steps and the step rate are controlled by clocks. the variation of the clock rate or the variation of the time between the two clock pulses determines the step rate. change in the step rate determines the acceleration, deceleration, and the slew rate in a given motion profile. figure 6 shows a typical trapezoidal motion profile. in the acceleration mode the step rate starts slowly and as the motion progresses the step rate increases according to a step rate table until it reaches the slew rate. at the slew rate the step rate is fixed and the period of the step clocks is constant. at the end of the slew rate the deceleration starts. in this part of the profile the step rate decreases according to a step rate table until the last step. the repeatability and accuracy of the step clocks in a stepper motor plays a major role in the stepper motor performance. one step time step clock from psd503 timer phase a phase b figur e 5. t iming diagram for a stepper motor contr ol
psd5xx ?application note 042 4-301 figure 7 shows the programmable pld (ppld) macrocell for each counter/timer block diagram in the psd5xx. in this design the four 16 bit timers on the psd5xx are used to control a four axis stepper motor under microprocessor control. the four 16-bit timers in the psd5xx are configured in the pulse mode. the timers are loaded with a given step count for the duration of a pulse. when the pulse duration has expired, the logic on the psd5xx is programmed such that the respective timer is preloaded with the count from the image registers. by preloading the timer, the step pulse duration will be exact with respect to the applied clock frequency. the timer clocks are configured to run at 1-mhz. in this case the preloading time on this system is based on a ?ne step ahead?stepper motor control. on the ramp up and ramp down mode each step clock will be preloaded in the image register because of the step rate changes. when the time for each step has expired the respective timer automatically preloads the image register in the count register and continues the new count. in this design the terminal count outputs (tc0 ?tc3) of the timers are routed to the four inputs (int0?int3) of the interrupt controller on the psd5xx device. the timer outputs are inverted and connected to the timer macrocell outputs mc2tmrx (x = 0 ?3 for three timers) in the ppld logic. figure 8 shows a simplified block diagram for the four axis stepper motor control. step clocks ramp up slew rate ramp down motor velocity profile profile time figur e 6. t ypical t rapezoidal speed pr ofile stepper motor clock generation by using a psd5xx (cont.)
4-302 psd5xx ?application note 042 and array timer [ 3 : 0 ] in clkin reset wdog2pld (internal feedback) polarity select counter / timer bit 5 of command register zpld input bus pin or macrocell select input mux comb / reg select mux pr d q q c timer _clock (prescaled clk) mc2tmr * timer input pin pt t 0 pt t? * * these are four similar macrocells with outputs mc2tmr [ 3:0 ] .abl file figur e 7. ppld macr ocell for each counter / t imer stepper motor clock generation by using a psd5xx (cont.)
psd5xx ?application note 042 4-303 sram psd503 17 bits address 16 bits address / data bus control signals & interrupt timers [ 0:3 ] outputs & logic control bus 80c186 microprocessor logic for stepper motor control axis # 1 power amp # 1 power amp # 2 power amp # 3 power amp # 4 axis # 2 axis # 3 axis # 4 stepper # 1 stepper # 2 stepper # 3 stepper # 4 figur e 8. simplified block diagram for the system stepper motor clock generation by using a psd5xx (cont.) the output of the psd5xx interrupt controller is connected to one ot the interrupt inputs on the 80c186 microprocessor. the psd5xx interrupt controller interrupts the microprocessor in response to the timer underflow. in response to this interrupt, the microprocessor reads the interrupt priorty status register and updates the respective timer image register. the output of a timer makes a high to low transition when a timer count expires.the high to low transition of the timer is inverted and is used to preload the respective timer from the last image register. in the slewing mode the image register for a timer does not need to be preloaded on each step interrupt. as the timer count expires the old count will be pre-loaded automatically. figure 9 shows the logic configuration for a given axis and figure 10 shows the *.abl file listing for the preloading capability of the timers.
4-304 psd5xx ?application note 042 counter start counter (bit 1 of global command register) counter output (port a or b) output polarity select (bit 3 of cmd register) software freeze ( freeze command register) timer_clock software select bit (bit 2 of cmd register) enable command (bit 7 of cmd register) pin or macrocell (selected by bit 5 of cmd register) software gating bit (bit 6 of cmd register) increment/decrement select (bit 1 of cmd register) software load (software load / store register) terminal count (tc) to interrupt controller freeze acknowledge (status flags register) load / store enable/disable terminal count (tc) to port e figur e 9. logic configuration for psd5xx in pulse mode stepper motor clock generation by using a psd5xx (cont.)
psd5xx ?application note 042 4-305 stepper motor clock generation by using a psd5xx (cont.) figur e 10. a sample ppld configuration in an *.abl file for the psd5xx ?pld equation f or the timer to preload mc2tm r 0 = ( ! timerou t 0); mc2tm r 1 = ( ! timerou t 1); mc2tm r 2 = ( ! timerou t 2); mc2tm r 3 = ( ! timerou t 3); figure 11 shows a block diagram of a psd5xx family product. in this design the psd503 is used. the psd503 is configured to 64k x 16 eprom in mux mode. the address and data on the 80c186 are multiplexed so the psd503 latches the address internally. the address lines a16 and a17 are internally latched using pa6 and pa5 from the psd503 ports. ports pc0 pc7, pd0 ?pd7, pe3 and pe4 on the psd503 are used to output the address a0 a17 externally to be used by the 128k x 16 sram external to the psd503 device. pa0 through pa3 are used as timer outputs to provide clocks for the stepper motor control. figure 12 shows the schematic for the processor connection to the psd503 and figure 13 shows a schematic for a typical stepper motor control unit interface to the psd503. the stepper motor interface control uses pb0 ?pb5 to control the four l297 stepper motor control chips. pb0 and pb1 are used to enable and disable the four axis of the motion. pb2 through pb5 are used to control the direction of the motor motion. pb0 through pb7 are configured in the software. figure 14 shows the *.abl file used in this design. 80c186 inter face to the psd503
4-306 psd5xx ?application note 042 prog. bus intrf adio port control rd, wr ad0 ?ad15 pc0 ?pc7 pd0 ?pd7 clkin watch dog output interrupt output clkin 60 clkin terminal counts page reg. zpld input bus global config. & security prog. port port a prog. port port b power manager unit vstdby pa0 ?pa7 pb0 ?pb7 prog. port port e prog. port port d prog. port port c pe0 ?pe7 address / data / control bus 4 macrocells 2 macrocells 8pt 4pt 2pt port a macrocells port b macrocells port e macrocells 27pt 61 60 80pt 11pt clkin four 16 - bit 256k 1m bit eprom 16 k bits sram i/o decoder eprom select sram select peripheral selects macrocell feedback or port input csiop general pld (gpld) peripheral pld (ppld) interrupt controller counter/ timers 24 macrocells decode pld (dpld) figur e 11. psd5xx block diagram
psd5xx ?application note 042 4-307 figur e 12. schematic for the psd503 inter face to a 80c186 pr ocessor d0 d1 d2 d3 d4 d5 d6 d7 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 24 29 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 22 30 24 29 u12 ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 pe0 pe1/ ale pe2 pe3 pe4 pe5 pe6 pe7 rd wr reset csi clkin gnd gnd gnd gnd vstdby 186 _ ad0 186 _ ad1 186 _ ad2 186 _ ad3 186 _ ad4 186 _ ad5 186 _ ad6 186 _ ad7 186 _ ad8 186 _ ad9 186 _ ad10 186 _ ad11 186 _ ad12 186 _ ad13 186 _ ad14 186 _ ad15 186 _ a16 186 _ a17 pcs3 186 _ a0 186 _ a1 186 _ a2 186 _ a3 186 _ a4 186 _ a5 186 _ a6 186 _ a7 186 _ a8 186 _ a9 186 _ a10 186 _ a11 186 _ a12 186 _ a13 186 _ a14 186 _ a15 wsi _ t0 wsi _ t1 wsi _ t2 wsi _ t3 step _ d0 step _ d1 step _ d2 step _ c3 step _ e0 step _ e1 pcs2 x 1 x 2 t i 0 t i 1 res test drq0 drq1 int0 int1 int2 / ta0 int3 / ta1 ardy srdy nmi hold mcs0 mcs1 mcs2 mcs3 pcs0 pcs1 pcs2 pcs3 pcs4 pcs5 /a1 pcs6 /a2 17 15 13 11 8 6 4 2 15 14 12 10 7 5 3 1 68 67 66 65 64 61 63 62 22 23 34 33 52 53 54 56 57 51 40 39 48 18 52 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 v cc v cc pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 38 37 36 34 33 32 31 30 41 29 40 39 42 1 35 19 51 28 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 cs1 cs2 oe we a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 cs1 cs2 oe we 186 _ a1 186 _ a2 186 _ a3 186 _ a4 186 _ a5 186 _ a6 186 _ a7 186 _ a8 186 _ a9 186 _ a10 186 _ a11 186 _ a12 186 _ a13 186 _ a14 186 _ a15 186 _ a16 186 _ a17 186 _ a1 186 _ a2 186 _ a3 186 _ a4 186 _ a5 186 _ a6 186 _ a7 186 _ a8 186 _ a9 186 _ a10 186 _ a11 186 _ a12 186 _ a13 186 _ a14 186 _ a15 186 _ a16 186 _ a17 186 _ ad0 186 _ ad1 186 _ ad2 186 _ ad3 186 _ ad4 186 _ ad5 186 _ ad6 186 _ ad7 186 _ ad8 186 _ ad9 186 _ ad10 186 _ ad11 186 _ ad12 186 _ ad13 186 _ ad14 186 _ ad15 13 14 15 17 18 19 20 21 13 14 15 17 18 19 20 21 d0 d1 d2 d3 d4 d5 d6 d7 u14 u56 +5v +5v +5v +5v +5v 14 +5v rp3 r pack 1 2 3 4 5 6 7 8 9 10 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 /s3 a17/s4 a18 /s5 a19 /s6 bhe /s7 ale/ qs0 wr / qs1 rd/ qsmd to0 to1 ucs lcs s0 s1 s2 clko reset hlda dt/ r den lck 7 8 1 u13 u57 clock osc 16 m rst_188 r 23 4.7k r24 4.7k pcs0 pcs1 pcs2 pcs3 pcs4 pcs5 pcs6 psd5xx 80186 m b841000 80 m b841000 80 186 _ ad (0 ... 15) pcs (0 ... 6) 186 _ a ( 0 ... 117 ) 186 _ a ( 0 ...17 ) wsi_t ( 0 ... 3 ) step_d ( 0 ... 3 ) step_e ( 0 ... 1 ) 186 _ ad0 186 _ ad1 186 _ ad2 186 _ ad3 186 _ ad4 186 _ ad5 186 _ ad6 186 _ ad7 186 _ ad8 186 _ ad9 186 _ ad10 186 _ ad11 186 _ ad12 186 _ ad13 186 _ ad14 186 _ ad15 wsi_t ( 0 ... 3 ) step_d ( 0 ... 3 ) step_d ( 0 ... 1 ) 59 58 20 21 24 47 18 19 45 44 42 41 55 49 46 50 38 37 36 35 25 27 28 29 30 31 32
4-308 psd5xx ?application note 042 figur e 13. schematic inter face between psd503 and the l297 stepper contr oller 12 16 15 1 19 11 10 17 18 20 14 13 2 v cc osc vref sync h/f cntrl en cw/ccw clk res s1 s2 gnd 4 6 7 9 a b c d i n h 1 i n h 2 home u7 5 8 3 12 16 15 1 19 11 10 17 18 20 14 13 2 v cc osc vref sync h/f cntrl en cw/ccw clk res s1 s2 gnd 4 6 7 9 a b c d i n h 1 i n h 2 home u7 l297 l297 l297 l297 5 8 3 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 12 16 15 1 19 11 10 17 18 20 14 13 2 v cc osc vref sync h/f cntrl en cw/ccw clk res s1 s2 gnd 4 6 7 9 a b c d i n h 1 i n h 2 home u7 5 8 3 12 16 15 1 19 11 10 17 18 20 14 13 2 v cc osc vref sync h/f cntrl en cw/ccw clk res s1 s2 gnd 4 6 7 9 a b c d i n h 1 i n h 2 home u7 5 8 3 amp for stepper # 1 amp for stepper # 2 amp for stepper # 3 amp for stepper # 4 wsi _ t ( 0 ... 3 ) wsi _ t ( 0 ... 3 ) step1 _ c ( 0...2 ) step _ reset step _ d ( 0...3 ) step _ e ( 0...1 ) step _ d ( 0...3 ) step _ e ( 0...1 ) c7 3.3 pf r12 r11 r r r r r r r r21 r22 r31 r32 r41 r42 r7 22 k +5v +5v +5v +5v +5v +5v +5v +5v step _ e0 step _ d1 wsi _ t1 step _ e1 step _ d0 wsi _ t0 step _ e1 step _ d2 wsi _ t2 step _ e1 step _ d3 wsi _ t3 jp1 conn 4 jp2 conn 4 jp3 conn 4 jp4 conn4 stepper motor = 4 connection stepper motor = 3 connection stepper motor = 2 connection stepper motor = 1 connection
psd5xx ?application note 042 4-309 figur e 14. pr ogram listing for the abel file used in this design 80c186 inter face to the psd503 (cont.) module mfhs_16 title ?esign for psd503 abel source file to interface with 80c186? ?nput signals ?ddress lines, using reserved names. a15,a14,a13,a12,a11,a10,a9,a8,a1,a0 pin; wr pin; rd pin; bhe pin; a16 pin 21; ?igh order address input a17 pin 22; ?igh order address input add_16 pin 34; ?ddress 16 latched output add_17 pin 31; ?ddress 17 latched output ?pins dedfined by npk umcs pin; ?upper memory chip select lmcs pin; ?lower memory chip select emcs pin; ?even memory chip select for external sram omcs pin; ?odd memory chip select for external sram pcs3 pin; ?psd upper 256 bytes address chip select space pcs2 pin; ?psd lower 256 bytes address chip select space pb0, pb1, pb2, pb3, pb4, pb5 pin; ?stepper motor control port ?timer contol pins timerout0 pin; ?stepper 1 clock 1 timerout1 pin; ?stepper 2 clock 2 timerout2 pin; ?stepper 3 clock 3 timerout3 pin; ?stepper 4 clock 4 ?port control pd0, pd1, pd2, pd3, pd4, pd5, pd6, pd7 pin; ?upper address output pc0, pc1, pc2, pc3, pc4, pc5, pc6, pc7 pin; ?lower address output clkin, reset pin; ?sing the reserved names. ?utput signals csiop, rs0, es0, es1, es2, es3 node ; ?pld output chip selects mc2tmr0 node; ?ppld output to timer 0 mc2tmr1 node; ?ppld output to timer 1 mc2tmr2 node; ?ppld output to timer 2 mc2tmr3 node; ?ppld output to timer 3
4-310 psd5xx ?application note 042 80c186 inter face to the psd503 (cont.) figur e 14. pr ogram listing for the abel file used in this design (cont.) ?eneral outputs ?efinitions ?age = [pgr3,pgr2,pgr1,pgr0]; ck = .c. ; ?clock pulse definition x = .x. ; ?don? care address = [a16,a15,a14,a13,a12,a11,a10,a9,a8,x,x,x,x,x,x,a1,a0]; add = [pc7,pc6,pc5,pc4,pc3,pc2,pc1,pc0]; equations ?pld equations csiop = ((address >= ^h00100) & (address <= ^h001f f )); rs0 = 0; ?disable the 2k on board sram es0 = (address >= ^h00000) & (address <= ^h07ff f ) & (!umcs); ?32k block 0 es1 = (address >= ^h08000) & (address <= ^h0fff f ) & (!umcs); ?32k block 1 es2 = (address >= ^h10000) & (address <= ^h17fff) & (!umcs); ?32k block 2 es3 = (address >= ^h18000) & (address <= ^h1ffff) & (!umcs); ?32k block 3 add_16 = a16; ?address 16 latched output add_17 = a17; ?address 17 latched output emcs = (!lmcs & bhe & !a0) + (!lmcs & !bhe & !a0); ?even address sram chip select omcs = (!lmcs & !bhe & a0) + (!lmcs & !bhe & !a0); ?odd address sram chip select ?pld equations mc2tmr0 = (!timerout0); ?pre load timer 0 mc2tmr1 = (!timerout1); ?pre load timer 1 mc2tmr2 = (!timerout2); ?pre load timer 2 mc2tmr3 = (!timerout3); ?pre load timer 3 ?***************************************************************************************************** ? test vectors ?***************************************************************************************************** end mfhs_16
psd5xx ?application note 042 4-311 figur e 15. block diagram for the register configuration and inter r upt operation 80c186 inter face to the psd503 (cont.) psd503 timer initialization load command register for each timer by 0x99 read interrupt read register to clear all interrupts select all interrupt inputs to rising edge unmask the timer interrupt in mask register configure the 80c186 interrupt load counter count register with new count load image register for the timers set dlcy register to 0 x 04 select port a for timer output load image register for the timers select software load/start for the start up enable the timers from global register enable the respective timer for operation wait for interrupt read interrupt priority register determine the respective timer interrupt load the respective image register for the timer no interrupt occurred? yes
4-312 psd5xx ?application note 042 figur e 16. a sample *.c pr ogram for this application (cont.) 80c186 inter face to the psd503 (cont.) #include #include #include #include typedef unsigned short ushort; typedef short short; typedef unsigned long* pulong; #include ?_step.dat /* stepper profile table */ #define pcs0 0x000 #define pcs1 0x080 #define pcs2 0x100 #define pcs3 0x100 #define pcs4 0x200 #define pcs5 0x280 /* wsi registers */ #define wsiintrread pcs2+0xd4 /* interrupt read clear */ #define wsiintrmask pcs2+0xd3 /* interrpt mask register */ #define wsiintrmode pcs2+0xd2 /* interrupt edge/level */ #define wsiintrreq pcs2+0xd1 /* interrupt request latch */ #define wsiintrpri pcs2+0xd0 /* interrupt priority */ #define wsislr pcs2+0xa5 /* software load/stor */ #define wsicntr0 pcs2+0x98 /* timer 0 control */ #define wsicntr1 pcs2+0x9a /* timer 1 control */ #define wsicntr2 pcs2+0x9c /* timer 2 control */ #define wsicntr3 pcs2+0x9e /* timer 3 control */ #define wsicmd0 pcs2+0xa0 /* timer 0 control register */ #define wsicmd1 pcs2+0xa1 /* timer 1 control register */ #define wsicmd2 pcs2+0xa2 #define wsicmd3 pcs2+0xa3 #define wsidlcy pcs2+0xa6 /* scale factor control of timers */ #define wsiimg0 pcs2+0x90 /* timer 0 image register*/ #define wsiimg1 pcs2+0x92 /* timer 1 image register*/ #define wsiimg2 pcs2+0x94 /* timer 0 image register*/ #define wsiimg3 pcs2+0x96 /* timer 1 image register*/ #define wsiglbreg pcs2+0xa8 /* timers global register */ #define wsisfr pcs2+0x08 /* special function register for port a */ #define wsifreez pcs2+0xa4 #define wsiportb_cntr pcs2+0x03 /* port b configuration */ #define wsiportb_dir pcs2+0x07 #define wsiportc_cntr pcs2+0x12 /* port c configuration */ #define wsiportc_dir pcs2+0x16 #define wsiportd_cfg pcs2+0x13 /* port d configuration */ #define wsiportd_dir pcs2+0x17 #define wsiporte_sfr pcs2+0x28 /* port e configuration */ #define wsiporte_dir pcs2+0x26
psd5xx ?application note 042 4-313 figur e 16. a sample *.c pr ogram for this application (cont.) 80c186 inter face to the psd503 (cont.) #define wsiporte_out pcs2+0x24 #define wsiporte_in pcs2+0x20 #define wsiporte_cfg pcs2+0x22 #define pulse_mode_disabled 0x99 /* was 99 */ #define enable 0x04 /* was 00*/ /* 188 registers */ #define i0con 0xff38 #define i1con 0xff3a #define imask 0xff28 #define eoi 0xff22 /* global variables here */ int stepper_1_total_step_count; int step_1_max_slew_count; int step_1_motion_index; int step_1_motion_stat; int step_1_slew_count; int stepper_1_ramp_up_count; int stepper_1_ramp_down_count; int stepper_1_step_count; int stepper_1_step_time; int step_1_time; int step_1_count_old; int stepper_1_profile[20]; } ushort image; ushort motornum; /* interrupt 1 routine */ ushort port = wsiintrread; ushort iw; void _interrupt wsihandler(void) { static ushort read; image = 0x200; switch( inportb(wsiintrpri) & 0x07) {
4-314 psd5xx ?application note 042 figur e 16. a sample *.c pr ogram for this application (cont.) 80c186 inter face to the psd503 (cont.) case 0: outport(wsiimg0, step_1_time); /* load timer 0 for step pulse */ stepper_1_step_count++; break; case 1: outport(wsiimg1, image); break; case 2: outport(wsiimg2, image); break; case 3: outport(wsiimg3, image); break; } outport(eoi,0x8000); _enable(); } void init_timers(void) { pulong pivt=null; _disable(); image = 100; /* pulse mode timer 0-3 */ outportb(wsicmd0, 0x99); /* program command register for the counters */ outportb(wsicmd1, 0x99); /* all counters to pulse mode */ outportb(wsicmd2, 0x99); /* all counters disabled */ outportb(wsicmd3, 0x99); /* interrupt wsi setup */ inportb( wsiintrread); /* clear all the interrupts */ outportb(wsiintrmode,0x00); outportb(wsiintrmask,0x0f); /* unmask timers interrupt */ outportb(wsiporte_sfr,0x0d); /* confgure port e for special function */ /* interrupt 188 setup */ pivt[12] = (pulong)sensorint0; /* sensor interrupt */ outport b (i0con,0x012); /* disable sensor inerrupt */ pivt[13] = (pulong)wsihandler; /* interrupt # 1 initilization */ outport b (i1con,0x010); /* was level sensetive 0x07 */ outport b (imask,0xdd); image = 0;
psd5xx ?application note 042 4-315 figur e 16. a sample *.c pr ogram for this application (cont.) 80c186 inter face to the psd503 (cont.) outport(wsicntr0, 0x00); outport(wsicntr1, 0x00); outport(wsicntr2, 0x00); outport(wsicntr3, 0x00); outportb(wsidlcy, 0x04); outportb(wsisfr, 0x0f); outport( wsiimg0, image+0x340); outport( wsiimg1, image+0x300); outport( wsiimg2, image+0x260); outport( wsiimg3, image+0x220); outportb(wsislr,0x0f); outportb(wsiglbreg,0x02); /* configure the wsi global register */ _enable(); /* enable interrupt */ } /* this routine sets up timer 0 for the start up profile */ void step_1_init(void) { static short s_en1,s1_c; static short c_r1,c_r2,m_c; stepper_1_step_count = 0; step_1_count_old = 0; stepper_1_step_count = 0; stepper_1_total_step_count =1000; step_1_max_slew_count = 998; step_1_motion_index = 0; step_1_slew_count = 0; stepper_1_ramp_up_count = 5; stepper_1_ramp_down_count = 7; step_1_motion_stat = 0; /* set up for ramp up */ step_1_time = 0x3000; outportb(step_motor1_control,s_en1); /* reset motor state */ outportb(wsicmd0, 0x9d); /* enable timer 0 for stepper 1 */ } /* this routin is used to update the profile table for motor 1 */ void stepper_1_move(void) { if( stepper_1_step_count > step_1_count_old ) {
4-316 psd5xx ?application note 042 figur e 16. a sample *.c pr ogram for this application (cont.) 80c186 inter face to the psd503 (cont.) i f ( step_1_motion_stat == 0 ) { step_1_motion_index++; /* ***** ramp up stepper 1 ***** */ step_1_time = x_axis[step_1_motion_index]; if( step_1_motion_index == 132 ) { step_1_motion_stat = 1; /* set status for slew */ } } if( step_1_motion_stat == 1 ) { step_1_slew_count++; /* ***** slew for stepper 1 ***** */ if( step_1_slew_count = = step_1_max_slew_count ) { step_1_motion_stat = 2; /* set status for ramp down */ step_1_motion_index = 132; } } if( step_1_motion_stat == 2 ) { step_1_motion_index? /* ***** ramp down for stepper 1 ***** */ if( step_1_motion_index != 0 ) { step_1_time = x_axis[step_1_motion_index]; } i f ( step_1_motion_index == 0 ) { stepper_1_step_count = 0; step_1_count_old = 0; outportb(wsicmd0, 0x99); /* disable motor */ outportb(wsicmd0, 0x99); /* disable motor. this is just for ice */ } } step_1_count_old = stepper_1_step_count; } } }
psd5xx ?application note 042 4-317 figur e 16. a sample *.c pr ogram for this application (cont.) 80c186 inter face to the psd503 (cont.) main ( ) { static ushort read, y, d1=0xaa,d2=0xaa; static ushort key; init_timers ( ); step_1_ini t ( ); key = 1; while(1) { switch( key ) { case 1: stepper_1_move ( ); break; case 2: stp_2 ( ); break; case 3: dcm_1 ( ); break; case 4: dcm_2 ( ); break; case 5: cres_12 ( ); break; case 6: c188_152 ( ); break; } } return 0; }
4-318 psd5xx ?application note 042 softwar e configuration of the psd503 figure 15 shows a block diagram of the steps needed to configure the registers of the psd503 for this application. figure 16 shows a sample software program written in c that is used in this application to configure the psd503. this software programs the special function register of port a to be used as the timer outputs. figure 17 shows the psdsoft configuration of the timers. the psd503 must be configured through psdsoft for the bus type, wr, rd, intr and port operation. the timer clock frequency is configured through the dlcy register to 1mhz. as the step rate increases the step rate accuracy deteriorates due to the quantization effect. the quantization effect is not a problem in this application. the output pulse width of each timer is one microsecond which is sufficient for this application. counter / timer 0: waveform/pulse mode. counter / timer 1: pulse output. counter / timer 2: waveform/pulsemode. counter / timer 3: pulse output do you need automatic power down clock input ? no do you want to set the security bit ? no do you need the intr output signal ? yes figur e 17. psdsoft configuration of the t imers conclusion in this application the psd503 provided a very useful integrated means of design. the following were benefited from this design: 64 k x 16 eprom eighteen bits of latched output for demultiplexing address from data. an 8-bit interrupt controller equivalent to an 8259. four 16-bit preloadable timers with a prescaler for the timer clocks. logic for decoding. programmable external ports. the board space reduction and the amount of noise reduction that resulted from this design is immeasurable.
psd5xx ?application note 042 4-319 design for psd503 abel sour ce file to inter face with 80c186 ******************************************************************************************************* w s i - psdsoft version 1.05b output of psd fitter ******************************************************************************************************* title : design for psd503 abel source file to interface with 80c186 project : mfhs_16 date : 04/07/1995 device : psd503b1 time : 09:31:05 fit option : keep current ******************************************************************************************************* pin assignment 1 ] gnd gnd [35 address/data bus adio_7 2 ] adio7 pe2 [36 introut address/data bus adio_6 3 ] adio6 pe1 [37 ale address/data bus adio_5 4 ] adio5 pe0 [38 bhe address/data bus adio_4 5 ] adio4 csi [39 csi address/data bus adio_3 6 ] adio3 reset [40 reset address/data bus adio_2 7 ] adio2 rd [41 rd address/data bus adio_1 (a1) 8 ] adio1 clkin [42 clkin address/data bus adio_0 (a0) 9 ] adio0 pb7 [43 pcs2 pc7 10] pc7 pb6 [44 (not used) pc6 11] pc6 pb5 [45 pb5 pc5 12] pc5 pb4 [46 pb4 pc4 13] pc4 pb3 [47 pb3 pc3 14] pc3 pb2 [48 pb2 pc2 15] pc2 pb1 [49 pb1 pc1 16] pc1 pb0 [50 pb0 pc0 17] pc0 gnd [51 18] vcc vcc [52 19] gnd pd7 [53 pd7 umcs 20] pa7 pd6 [54 pd6 a16 21] pa6 pd5 [55 pd5 a17 22] pa5 pd4 [56 pd4 omcs 23] pa4 pd3 [57 pd3 timerou t 3 24] pa3 pd2 [58 pd2 timerou t 2 25] pa2 pd1 [59 pd1 timerou t 1 26] pa1 pd0 [60 pd0 timerou t 0 27] pa0 adio15 [61 address/data bus adio_15 (a15) 28] vstby adio14 [62 address/data bus adio_14 (a14) wr 29] wr adio13 [63 address/data bus adio_13 (a13) pcs3 30] pe7 adio12 [64 address/data bus adio_12 (a12) add_17 31] pe6 adio11 [65 address/data bus adio_11 (a11) imcs 32] pe5 adio10 [66 address/data bus adio_10 (a10) emcs 33] pe4 adio9 [67 address/data bus adio_9 (a9) add_16 34] pe3 adio8 [68 address/data bus adio_8 (a8) global configuration data bus : 16 multiplexed ale/as signal : active high watchdog mode : off security protection : off address & data bus assignment stimulus bus name signal description `adiol = adio[7:0] = address/data bus adio_7 ?adio_0 `adioh = adio[15:8] = address/data bus adio_15 ?adio_8 adio = adio[15:0] = address/data bus adio_15 ?adio_0
4-320 psd5xx ?application note 042 resour ce usa g e summar y device resources use d / total percentage port a: (pin 20 ?pin 27) i/o pins 8 / 8 100 % mcu i/o or address out 0 / 8 0 % peripheral i/o 0 / 8 0 % zpld inputs 3 / 8 37 % zpld combinatorial outputs 1 / 8 12 % zpld registered outputs 0 / 8 0 % other information buried macrocells 0 / 7 0 % product terms 1 / 27 3 % timer outputs 4 / 4 100 % port b: (pin 43 - pin 50) i/o pins 7 / 8 87 % mcu i/o or address out 7 / 8 87 % zpld inputs 0 / 8 0 % zpld combinatorial outputs 0 / 8 0 % zpld registered outputs 0 / 8 0 % other information buried macrocells 0 / 8 0 % product terms 0 / 80 0 % timer outputs 0 / 4 0 % port c: (pin 10 - pin 17) i/o pins 8 / 8 100 % mcu i/o or address out 8 / 8 100 % zpld input pins 0 / 8 0 % data port (non-mux bus) 0 / 8 0 % port d: (pin 53 - pin 60) i/o pins 8 / 8 100 % mcu i/o or address out 8 / 8 100 % zpld input pins 0 / 8 0 % data port (16-bit non-mux bus) 0 / 8 0 % port e: (pin 30 - pin 34, pin 36 - pin 38) i/o pins 8 / 8 100 % mcu i/o or address out 1 / 8 12 % zpld inputs 1 / 8 12 % zpld combinatorial outputs 3 / 8 37 % zpld registered outputs 0 / 8 0 % control signal inputs 2 / 2 100 % timer control inputs 0 / 4 0 % interrupt control output 1 / 1 100 % apd clock input 0 / 1 0 % terminal counts (tc) 0 / 4 0 % other information buried macrocells 0 / 5 0 % product terms 3 / 11 27 % counter/timer: embedded nodes product terms 4 / 8 50% interrupt: embedded nodes product terms 0 / 4 0% design for psd503 abel sour ce file to inter face with 80c186 (cont.)
psd5xx ?application note 042 4-321 omc resource assignment resources used user name port a : macro cell 4 omcs (mc_pa4) => combinatorial port b: port e: macro cell 3 add_16 (mc_pe3) => combinatorial macro cell 4 emcs (mc_pe4) => combinatorial macro cell 6 add_17 (mc_pe6) => combinatorial equations dpld equations: es0 = !a15 & !a16 & !umcs; es1 = a15 & !a16 & !umcs; es2 = !a15 & a16 & !umcs; es3 = a15 & a16 & !umcs; rs0 = 0; csiop = !a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & a8 & !a16; timer equations: mc2tmr0 = !timerout0; mc2tmr1 = !timerout1; mc2tmr2 = !timerout2; mc2tmr3 = !timerout3; interrupt equations: port a equations: omcs = !bhe & !lmcs; [omcs].oe = 1; port b equations: port e equations: add_16 = a16; emcs = !a0 & !lmcs; add_17 = a17; [add_16, emcs, add_17].oe = 1; design for psd503 abel source file to interface with 80c186 (cont.) return to main menu

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